Xilinx Vivado 2017.4 Site

: Users can specify AXI4 master and slave Lite interfaces directly using the INTERFACE directive .

: ERROR: [DRC DCI-3] when using multiple I/O banks with different voltages. Workaround : In the XDC constraint file, add: xilinx vivado 2017.4

The IP Integrator (IPI) flow in 2017.4 was highly stable. It offered a seamless way to connect the Processing System (PS) with the Programmable Logic (PL) on Zynq devices. The automation for adding AXI interconnects and smart connects was mature enough to handle complex block designs without the frequent "board flow" bugs that plagued earlier versions. : Users can specify AXI4 master and slave